Socionext expects up to 5X productivity from Cadence's AI agent on a 3nm chip; Cadence reports October 26

Socionext expects up to 5X productivity from Cadence's InnoStack agent on the physical design of a 3nm SoC, announced six days before Cadence's Q3 report. After Moonshot's Kimi K3 designed a chip with no licensed EDA software at all, the duopoly needs named customers like this.

Vincent JiangVincent Jiang · 3 min read
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Anirudh Devgan, chief executive of Cadence Design Systems, presenting an update on machine learning for chip design
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Cadence chief executive Anirudh Devgan. Socionext's InnoStack deployment lands six days before Cadence's Q3 report on October 26.

A named customer, a 3nm chip and a 5X claim

Socionext−2.77% — Socionext, down 2.77 percent today, a Yokohama custom-chip designer listed in Tokyo as 6526.T, said on October 20, 2026, that it is applying Cadence's−1.33% — Cadence's, down 1.33 percent today InnoStack AI Super Agent to the physical design of a large-scale 3nm SoC, and plans to extend it across its development projects 1. President and COO Hisato Yoshida expects "up to 5X overall productivity gains" from the agentic workflow 1.

The first jobs are floorplanning and custom timing checks, with Socionext's own design knowledge fed into the flow through retrieval-augmented generation 1. Cadence's Chin-Chi Teng, who runs the digital and signoff group, said the agent is open and extensible enough for customers to integrate their own methodologies 1.

Six days before the print that prices it

Licenses are 91% of Cadence's sales and Japan is 6.4% of revenue 2; the company carries a market cap of $87.99 billion 3. Q3 lands on Monday October 26, with consensus at $2.04 a share on $1.61 billion of revenue, against company guidance of $2.01–$2.07 3. The stock closed October 19 at $325.86, against a $406.24 average target from 25 analysts 2. Reported growth has already re-accelerated for three straight quarters, from 6.2% year over year in the December 2025 quarter to 24.2% in the June 2026 quarter 4.

Cadence revenue growth has re-accelerated three straight quarters into the Q3 print

  • Cadence revenue
  • Estimate
$1B$1.2B$1.4B$1.6B$1.8BQ3 '24Q1 '25Q3 '25Q1 '26Q3 '26E$1.61Breports October 26
Data
Cadence revenue
Q2 '24$1.06B
Q3 '24$1.22B
Q4 '24$1.36B
Q1 '25$1.24B
Q2 '25$1.28B
Q3 '25$1.34B
Q4 '25$1.44B
Q1 '26$1.47B
Q2 '26$1.58B
Q3 '26E (estimate)$1.61B
Quarterly revenue, calendar quarters, in US dollars. Reported quarters from Cadence SEC filings; the final point is analyst consensus for Q3 2026.4,3

July's 48-hour scare set the stakes

On July 17, Cadence and Synopsys−1.12% — Synopsys, down 1.12 percent today fell roughly 9% after Moonshot AI's Kimi K3 model autonomously designed a working chip in 48 hours using only open-source tools: a 4mm² die on an open 45nm cell library 5. The caveats matched the selloff. Forty-five nanometres is generations behind the 3nm and 2nm frontier where Cadence's engines sit, and Bloomberg Intelligence saw no immediate threat to either company's revenue 5. Its warning was narrower: AI is becoming the primary interface to design tools, which shifts software value up the stack 5.

Honda against an unnamed OpenAI model

Cadence's other named proof point is Honda R&D, which is evaluating the ChipStack RTL Generation Agent, launched September 22, on advanced automotive SoCs 62. Early evaluations averaged 24% less chip area and 18% less power than pure foundation-model code, with functionally accurate RTL 6.

Synopsys answered on September 30 with GPT-Synopsys, a multiyear model built with OpenAI$1.18T — OpenAI, private, latest valuation $1.18T, but its early engagements are with unnamed semiconductor customers and no public benchmarks exist 7. Synopsys's July autonomous debug workflows, already used by AMD+1.72% — AMD, up 1.72 percent today, cut cycle time 25–40% in early evaluations 7. Cadence also holds an InnoStack alliance with Japan's Rapidus 8.

Measured agent gains are 18 to 40 percent, against the 5X claim

0%10%20%30%40%Chip area (Honda R&D)Power (Honda R&D)Debug cycle, low (Synopsys)Debug cycle, high (Synopsys)40%24%18%
Data
Reduction vs baseline
Chip area (Honda R&D)24%
Power (Honda R&D)18%
Debug cycle, low (Synopsys)25%
Debug cycle, high (Synopsys)40%
Percent improvement in early customer evaluations: Cadence's ChipStack RTL Generation Agent at Honda R&D (chip area, power) and Synopsys's autonomous debug workflows (debug cycle time, low and high end of the reported range). Sources: Silicon Semiconductor; eWeek.6,7

What the October 26 call has to show

The 5X figure is Socionext's expectation, not a result Cadence has reported, and nothing yet shows agent adoption lifting license counts rather than trimming them. Monday's call is the first reading: whether Cadence puts a number on agent-driven demand, and whether Japan's 6.4% share of revenue grows. Five-times productivity is either a bigger Cadence bill or a smaller one, and the meter starts running Monday.

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